IndexDigitalClock Jitter Limit
Clock Jitter Limit
How much timing error a converter clock can have before it eats your resolution.
- SNR ceiling for this clock
- 98 dB
- 146 dB
Input
Good crystal oscillators sit under 1 ps. Recovered S/PDIF clocks can reach hundreds.
How it works
Timing error becomes amplitude error
A converter that samples a moment too early or too late reads the wrong voltage. The faster the signal is changing, the bigger the mistake. A sine of frequency has a maximum slope of , so random timing error with rms value produces noise that limits the signal-to-noise ratio to
That is why the line on the plot falls 20 dB for every tenfold increase in frequency: treble suffers first.
Jitter budget
Setting that ceiling equal to the ideal SNR of an -bit converter gives the most jitter the clock may have:
Limits of the model
The formula assumes a full-scale sine and wideband random jitter. Music rarely has full-scale content at 20 kHz, so real systems are more tolerant than the worst case suggests. Periodic jitter behaves differently: it creates discrete sidebands around each tone instead of a raised noise floor.